1. Field of the Invention
The present invention relates to a semiconductor memory which is applicable to, for example, a semiconductor disk device fabricated with a plurality of semiconductor memories, which is used in a fashion similar to a hard disk device.
2. Description of the Background Art
For example, laptop of personal computers include a memory space which can be extended by connecting a card-like semiconductor disk device to an extended connector slot which is adapted for connecting thereto a hard disk drive.
FIG. 2 shows an example of a semiconductor disk device which is used as an auxiliary memory device as mentioned above. In FIG. 2, the semiconductor disk device 1 comprises one or more memory module groups 2, a microcomputer 3, a host interface 4, a buffer memory 5 and a memory controller 6. Each of the memory module groups 2 comprises a plurality of memory modules 21-2n, each of which is constituted of a single chip of serial memory, such as flash memory, and has the same speed capability as the others. The memory modules 21-2n in the memory module group 2 are connected in common with a bidirectional data line LDAT and a clock signal line LCLK.
It is assumed that the memory module group 2 corresponds to a header in a hard disk device; each of the memory modules 21-2n to a cylinder in the hard disk device; and an internal storage area of each of the memory modules 21-2n to a predetermined number of sectors from one sector address to another, where n is an integer.
The memory modules 21-2n are provided for the semiconductor disk device 1, and upon receipt of serial data for control, including an address and a type of access, for example, they continuously write thereinto or read out thereof data corresponding to a sector, e.g. 536 bytes of data.
To effect a writing operation on the semiconductor disk device 1, there is a need to supply from a host computer, not shown, thereto a command including information such as a header number, a cylinder number, the first sector number, the number of writing sectors and the like, and an additional command for instructing a writing operation. After issuance of these commands, data are transferred after the lapse of a predetermined time corresponding to the seek time, the rotation time and the like.
Upon receipt of the commands through the host interface 4, the microcomputer 3 decodes and converts the commands into control information accessible to a memory module 2i, the control information including an indication designating a memory module 2i and an address designating a sector in that memory module 2i, into which data is to be written, where i is an integer between 1 and n, inclusive. The control information thus converted is supplied to the memory controller 6. On the other hand, transmitted data for writing is fed through the host interface 4 to the buffer memory 5.
The memory controller 6 sends out serial data for control, which consists of an address, a control signal for instructing writing and the like, over the bidirectional data line LDAT to a predetermined memory module group 2 in accordance with the control information outputted from the microcomputer 3, and then sends out a sector of data from the buffer memory 5 through a parallel-to-serial conversion on the bidirectional data line LDAT to the predetermined memory module group 2. This transfer is repeated on a sector-by-sector basis. When the serial data for control is sent out to the bidirectional data line LDAT, and when data to be written is sent out to the bidirectional data line LDAT, the memory controller 6 sends out, of course, a clock signal to the clock signal line LCLK in synchronism with those sending operations, so that data supplied from the host computer is written into the predetermined memory module 2i of the memory module group 2.
On the other hand, to effect a reading operation on the semiconductor disk device 1, there is a need to supply from a host computer, not illustrated, to the semiconductor disk device 1 a command including information such as a header No., a cylinder No., a top sector No., the number of writing sectors and the like, and an additional command for instructing a reading operation.
Upon receipt of the commands through the host interface 4, the microcomputer 3 decodes and converts the commands into control information accessible to a memory module 2i, the control information including an indication designating a memory module 2i and an address designating a sector in that memory module 2i, from which data is to be read out. The control information thus converted is supplied to the memory controller 6.
The memory controller 6 sends out serial data for control, which consists of an address, a control signal for instructing writing and the like, over the bidirectional data line LDAT to a predetermined memory module group 2 in accordance with the control information outputted from the microcomputer 3, and sends out a clock signal on the clock signal line LCLK to the predetermined memory module group 2 in synchronism with the serial data sending operation. Also after sending the serial data for control, the memory controller 6 continuously sends out the clock signal on the clock signal line LCLK to the predetermined memory module group 2 and receives data read out from a predetermined memory module 2i of the memory module group 2 in response to the clock signal. The received data are converted into parallel data and stored in the buffer memory 5 through the host interface 4. In this manner, the data stored in the buffer memory 5 are transferred via the host interface 4 to the host computer.
However, the semiconductor disk device 1 has a drawback in that a timing relation between transfer data and the clock signal deviates from a predetermined timing relation at a transfer destination (a memory module when writing, or a memory controller when reading) for the reasons as set forth below:
(1) It is difficult to avoid such a situation that the timing of the clock signal with respect to the timing of outputting data is outside a specified range due to an irregularity caused by manufacturing the memory controller;
(2) There exists a difference in performance between the memory modules owing to an irregularity in manufacturing the memory modules;
(3) The lengths of the signal line and the bidirectional data line, which are connected to a memory module, vary depending upon the position in which the memory module is loaded, and parasitic capacitance and resistance vary depending upon a path. These cause a delay in transferring the signals and data to vary; and
(4) The signal lines are mutually different in length, which are connected to associated memory modules even in the same memory module group depending upon the position in which the memory module is loaded, and parasitic capacitance and resistance vary depending upon a path. These also cause a delay in transferring the signals to vary; and
(5) It is difficult to avoid skewing of the delay in transferring the signals and data.
Consequently, when the transfer is effected in a certain timing, some memory module will encounter critical set-up and hold timings. Thus, there is a large possibility of malfunctions in writing and reading.
If all the memory modules were involved in the same timing deviation, it would be possible to avoid the above-mentioned inconvenience through, for example, regulating the phase of the clock signal outputted from the memory controller. However, for example, as shown in parts (a) and (b) of FIG. 3, while there is obtained a good timing on the memory module 2n which is located nearest to the memory controller 6, the memory module 21, which is located farthest from the memory controller 6, will encounter severe set-up and hold timing discrepancies, as shown in parts (c) and (d) of FIG. 3. Therefore, in such a case, it is impossible to apply the above-mentioned measure.
There is a way to prevent malfunctions at the time of writing and reading by means of providing a large margin of the set-up time and the hold time through elongating a cycle time or clock period. However, according to this way, there will occur another problem such that the transfer rate at the time of transfer from and to the memory module is reduced, and as a result the operational speed of the semiconductor disk device must be reduced.
This problem occurs on not only with the semiconductor disk device, but also the various kinds of semiconductor memories in which a plurality of memory modules share the data line and the clock signal line jointly with each other.